发表论文

Nanoscale Devices
The full text most of these papers may be found at the IEEE website at www.ieee.org.

D.H. Tassis, A. Tsormpatzoglou, C.A. Dimitriadis, G. Ghibaudo, G. Pananakakis, N. Collaert,
"Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs",
Microelectronic Engineering, Vol. 87, Issue 11, November 2010, pp. 2353-2357.

Guriqbal Singh Josan, Archana Devasia, Sean Rommel, Santosh K. Kurinec,
"Simulation and verification of void transfer patterning (VTP) technique for nm-scale features",
Microelectronic Engineering, In Press, Corrected Proof, Available online 27 August 2010.

Ping Bai, Hong Son Chu, Mingxia Gu, Oka Kurniawan, Erping Li,
"Integration of plasmonics into nanoelectronic circuits",
Physica B: Condensed Matter, Vol. 405, Issue 14, 15 July 2010, pp. 2978-2981.

F. Djeffal, M. Meguellati, A. Benhaya,
"A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs",
Physica E: Low-dimensional Systems and Nanostructures, Vol. 41, Issue 10, October 2009, pp. 1872-1877.

U. Monga, H. Børli, T.A. Fjeldly,
"Compact subthreshold current and capacitance modeling of short-channel double-gate MOSFETs",
Mathematical and Computer Modelling, In Press, Accepted Manuscript, Available online 30 September 2009

Servin Rathi, Jyotika Jogi, Mridula Gupta, R.S. Gupta,
"Modeling of hetero-interface potential and threshold voltage for tied and separate nanoscale InAlAs–InGaAs symmetric double-gate HEMT",
Microelectronics Reliability, In Press, Corrected Proof, Available online 11 August 2009

X. Loussier, D. Munteanu, J. L. Autran,
"Simulation study of circuit performances of independent double-gate (IDG) MOSFETs with high-permittivity gate dielectrics",
Journal of Non-Crystalline Solids, Vol. 355, Issues 18-21, 1 July 2009, pp. 1185-1188

K. Romanjek, L. Hutin, C. Le Royer, A. Pouydebasque, M. -A. Jaud, C. Tabone, E. Augendre, L. Sanchez, J.-M. Hartmann, H. Grampeix, V. Mazzocchi, S. Soliveres, R. Truche, L. Clavelier, P. Scheiblin, X. Garros, G. Reimbold, M. Vinet, F. Boulanger, S. Deleonibus,
"High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate",
Solid-State Electronics, Vol. 53, Issue 7, July 2009, pp. 723-729

M. Y. Yunus, M. Rusop,
"Effect of gate dielectric to the threshold voltage of 65 nm NMOS structure",
AIP Conference Proceedings, Vol. 1136, 2009, pp. 570-574

K. Modzelewski, R. Chintala, H. Moolamalla, S. Parke, D. Hackler,
"Design of a 32nm Independently-Double-Gated FlexFET SOI Transistor",
17th Biennial University/Government/Industry Micro/Nano Symposium, UGIM 2008. 13-16 July 2008, pp. 64-67

Shadi A. Dayeh, Darija Susac, Karen L. Kavanagh, Edward T. Yu, Deli Wang,
"Structural and room-temperature transport properties of zinc blende and wurtzite inas nanowires",
Advanced Functional Materials, Vol. 19, No. 13, July 10 2009, pp. 2102-2108

Qi Jianwen, Cheng Xiulan, Masayasu Tanjyo,
"Simulation on the effect of Halo implantation precision on the performance of 36NM NMOSFET device",
Semiconductor Technology, ISTC 2008 - Proceedings of the 7th International Conference on Semiconductor Technology, PV 2008-1, 2008, pp. 58-63

Suzhen Luan, Hongxia Liu, Renxu Jia, Naiqiong Cai, Jin Wang, Qianwei Kuang,
"Analytical model of drain current for ultra-thin body and double-gate schottky source/drain MOSFETs accounting for quantum effects",
Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, Vol. 29, No. 5, May 2008, pp. 869-874

S. Saurabh and M. Jagadesh Kumar,
"Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor:
Theoretical Investigation and Analysis",
Japanese Journal of Applied Physics, No. 48 (2009), pp. 064503-1.

M. Reyboz, P. Martin, T. Poiroux, O. Rozeau,
"Continuous model for independent double gate MOSFET",
Solid-State Electronics, In Press, Corrected Proof, Available online 28 March 2009.

T. Z. Mohamad, I. Ahmad, A. Zaharim,
"Optimum solution in fabricating 65 nm NMOS transistors using Taguchi method",
Advances on Applied Computer and Applied Computational Science. Proceedings of the 7th WSEAS International Conference on Applied Computer & Applied Computational Science (ACACOS '08), pp. 451-6, 2008.

S. Kolberg, H. Børli, and T. A. Fjeldly, "Modeling, Verification and Comparison of Short-Channel Double Gate and Gate-All-Around MOSFETs", J. Math. and Comp. in Simulation, in press

H. Børli, S. Kolberg, and T. A. Fjeldly, "Physics Based Current and Capacitance Model of Short-Channel Double Gate and Gate-All-Around MOSFETs", invited, Proc. IEEE Int. Conf. on Nanoelectronics, March 24-27, 2008, Shanghai, China, pp. 844-849. IEEE ref. 978-1-4244-1573-1/08.

H. Børli, S. Kolberg, T. Fjeldly, and B. Iñguez, "Current and Capacitance Modeling of Short-Channel DG MOSFETs", Proc. 7th Int. IEEE Caribbean Conf. on Devices, Circuits and Systems (ICCDCS'08), Cancun, Mexico, April 28-30, 2008, paper no. 19. IEEE ref. 978-1-4244-1957-9/08.

H. Børli, S. Kolberg, and T. A. Fjeldly, "Capacitance modeling of Short-Channel DG and GAA MOSFETs", invited paper, NSTI Nanotech 2008, Workshop on Compact Modeling, CRC Press, Boston, MA, June 1-5, 2008, vol. 3, pp. 745-749, 2008. ISBN: 978-1-4200-8505-1 (CD: ISBN 978-1-4200-8511-2)

H. Børli, K. Vinkenes, and T. A. Fjeldly, "Physics based Capacitance Modeling of Short-Channel Double-Gate MOSFETs", Physica Status Solidi (c), 1-4 (2008), in press. (DOI 10.1002/pssc.200780124)

S. Kolberg, H. Børli, and T. A. Fjeldly, "Compact Current Modeling of Short-Channel Multiple Gate MOSFETs", Physica Status Solidi (c), 1-4 (2008), in press. (DOI 10.1002/pssc.200880125)

H. Børli, S. Kolberg, and T. A. Fjeldly, "Capacitance Modeling of Short-Channel Double-Gate MOSFETs", Solid State Electronics, Vol. 52, pp. 1486-1490, 2008.

H. Børli, S. Kolberg, T. A. Fjeldly, and B. Iñguez, "Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs" IEEE Trans. Electron Devices, vol. 55, no.10, pp. 2678-2686, 2008.

T. A. Fjeldly and H. Børli, "2-D Modeling of Nanoscale Multigate MOSFETs", invited, Proc. 9th Int Conf. on Solid-State and Integr.- Circ. Techn. (ICSICT'08), Beijing, China, Oct. 2008.

Antonio Cerdeira, Benjamin Iniguez, Magali Estrada,
"Compact model for short channel symmetric doped double-gate MOSFETs,"
Solid-State Electronics, Vol. 52, Issue 7, Jul. 2008, pp. 1064-1070.

Sona P. Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta, R. S. Gupta
"Analytical modeling and simulation of subthreshold behavior in nanoscale dual
material gate AlGaN/GaN HEMT," Superlattices and Microstructures, Vol. 44, Issue
1, Jul. 2008, pp. 37-53.

Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R. S. Gupta
"Intermodulation distortion and linearity performance assessment of 50-nm gate
length L-DUMGAC MOSFET for RFIC design"
Superlattices and Microstructures, In Press, Corrected Proof, Available online 17 June 2008.

Chin Hong Teoh, R. Ismail,
"Device Design Consideration for Nanoscale MOSFET Using Semiconductor TCAD Tools,"
IEEE International Conference on Semiconductor Electronics, 2006. ICSE '06. Oct. 29 2006 - Dec. 1 2006, pp. 906 - 910.

A. K. Goel, H. Gopinathannair,
"Capacitance extraction for the nanoscale on-chip interconnects,"
IEEE International Conference on Semiconductor Electronics,
2004. ICSE 2004. 7-9 Dec. 2004 pp. 5.

Jaehong Lee, Junsoo Kim, Juhwan Jung, Seungbum Hong, Byung-Gook Park, Jong Duk
Lee, Hyungcheol Shin,
"A new resistive probe with higher resolution,"
IEEE Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. Vol. 1, 22-25
Oct. 2006, pp. 114 - 115.

C. Ravariu, A. Rusu, F. Udrea, F. Ravariu,
"Simulations results of some Diamond On Insulator nano-MISFETs" Diamond and Related Materials. Vol. 15, No. 4-8, Apr. - Aug. 2006, pp. 777-782.

V. Sverdlov, E. Ungersboeck, H. Kosina and S. Selberherr,
"Current transport models for nanoscale semiconductor devices",
Materials Science and Engineering: R: Reports, Vol. 58, Issue 6, 7 January 2008, pp. 228-270.

Abhinav Kranti and G. Alastair Armstrong,
"Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications", Microelectronic Engineering, Vol. 84, Issue 12, December 2007, pp. 2775-2784.

Chi-Woo Lee, Se-Re-Na Yun, Chong-Gun Yu, Jong-Tae Park and Jean-Pierre Colinge,
"Device design guidelines for nano-scale MuGFETs",
Solid-State Electronics, Vol. 51, Issue 3, March 2007, pp. 505-510.