MEDIA ALERT: Silvaco To Showcase Advanced Node Solutions At DAC 2016

7nm parasitic extraction, Custom design tools used for 10nm tapeout, Variation analysis and EM/IR capabilities, new FastSPICE and SRAM setup/hold characterization products

SANTA CLARA, Calif., –– May 24, 2016

WHO: Silvaco, Inc. today announced that it plans to showcase the company’s full TCAD-to-signoff tools with emphasis on advanced node capabilities at Design Automation Conference (DAC) 2016.


  • Monday, June 6, 2016
    • Exhibit Hours: 10:00 AM - 6:00 PM
    • Cocktails and Conversations!: 6:00 PM - 7:00 PM
  • Tuesday, June 7 2016
    • Exhibit Hours: 10:00 AM - 6:00 PM
    • Cocktails and Conversations!: 6:00 PM - 7:00 PM
  • Wednesday, June 8, 2016
    • Exhibit Hours: 10:00 AM - 6:00 PM


Visit Silvaco in booth #649 at the Austin Convention Center.
500 E Cesar Chavez Street
Austin, TX 78701


Silvaco technology experts will be available to discuss and demo our TCAD-to-signoff solutions with emphasis on new products and capabilities serving advanced process nodes.

  • FinFET RC parasitic extraction - MEOL/BEOL parasitics are critical at FinFET nodes and detailed analysis via 3D field solvers is required to accurately capture parasitic effects
  • OA iPDK support - iPDK support simplifies access to Silvaco’s custom design flow which are ideally suited for IoT process nodes, but are also being used at the most advanced nodes such as for 10nm analog IP development
  • Quick IR drop and EM analysis product used during layout to catch issues such as missing vias
  • FastSPICE for fast functional verification of SRAM and analog blocks that is becoming a significant challenge due to large extracted netlists at double patterned process nodes
  • Fully automated characterization of setup and hold for critical timing arcs for large extracted SRAMs
  • Variation analysis inclusive of Fast Monte Carlo, Statistical corners and High Sigma analysis for analog and memory designs
  • Statistical functional verification of standard cell libraries with reduction in time taken from weeks to days

Silvaco continues to collaborate with EDA and IP ecosystem partners some of whom will be presenting their solutions at our booth:

  • IPextreme
    • Together with its Constellations partners will showcase a broad portfolio of silicon-proven microprocessor, SoC infrastructure, automotive, and ESD/IO cores. In addition they will be demonstrating their latest IP management and IP compliance software.
  • Fieldscale
    • Will showcase parametric simulation of projected capacitive touchscreens, varying in controller, electrode pattern and dimensions, for several finger positions, parametric analysis of the effects of trace clearance and voltage level on the electric field in PCBs, and electrostatic simulation in ICs considering Line Edge Roughness (LER)
  • Coupling Wave Solutions
    • Will showcase early noise analysis capability used in CMOS/FDSOI technologies and fast SOI substrate noise and parasitic analysis that shrinks RF design time on SOI technologies

Partner Presentations

  • Silvaco will present at TSMC OIP Theater on all three exhibit days (times to be announced)

About Silvaco, Inc.

Silvaco, Inc. is a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Silvaco delivers a full TCAD-to-signoff flow for vertical markets including: displays, power electronics, optical devices, radiation & soft error reliability and advanced CMOS process and IP development. For over 30 years, Silvaco has enabled its customers to bring superior products to market at reduced cost and in the shortest time. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.