SILVACO TCAD and AMS Design Flows Adopted by VLSI Design and Education Center (VDEC)

Tokyo and Yokohama, Japan, January 18, 2005

VLSI Design and Education Center (VDEC), located in the University of Tokyo, and SILVACO Japan, Inc., a leading vendor of TCAD and analog/mixed-signal (AMS) electronic design automation (EDA) software, today announced that VDEC has adopted SILVACO’s complete TCAD and AMS design flow solutions to deliver its VLSI design instruction and chip fabrication services for leading national, public, private universities and colleges within Japan.

“VDEC is always committed to providing contemporary information and tools to the area of development education/research for LSI in our universities and technical colleges,” said Dr. Kunihiro Asada, Professor of Electronics and Director of VDEC. “As we start to provide a series of SILVACO software tools, we expect that the SoC/RF design environment, of rapidly increasing interest to universities will be further improved, based on miniaturization of the semiconductor manufacturing technology.”

“SILVACO is committed to supporting Japan’s excellent higher education system,” said Dr. Ivan Pesic, CEO of SILVACO Japan. “This partnership ensures that Japanese universities have the most advanced tools to train tomorrow’s engineers for the challenges they will face when they enter Japan’s pioneering semiconductor industry.”


Used by leading semiconductor companies in Japan, SILVACO TCAD tools include the ATLAS Device Simulator, ATHENA Process Simulator, and Virtual Wafer Fab Automation tools. SILVACO TCAD tools enable semiconductor engineers to create the processes and devices that are manufactured in Japan’s semiconductor factories.

SILVACO Analog/Mixed-Signal Design Tools

SILVACO analog/mixed-signal design tools include the very popular SmartSpice Circuit Simulator, Gateway Schematic Editor, Expert Layout Editor, Guardian DRC/LVS/LPE, and HIPEX Full-Chip Parasitic Extraction tools. SILVACO AMS tools enable IC designers to create semiconductor products with optimum semiconductor performance, lower development costs, reduced risks, and ultimately faster turn around time (TAT).

About VDEC

VDEC (VLSI Design and Education Center) are responsible for promotion of the development education/research for LSI in Japanese colleges/technically colleges highly at the national common facilities established in Tokyo University in 1996. We realize and operate the chip experimental production system with low-cost, using the latest semiconductor manufacturing technique as well as introduce the latest design tool environment in the block and provide them to users in universities/technical colleges across the country. We also organize seminars for the tools and the latest chip experimental production periodically. Now over 100 labs in nationwide universities/technical colleges are registered as users and produce over 400 kinds of chip a year, using wide range of CMOS technologies.

Address: Yayoi 2-11-16, Bunkyo-ku, Tokyo,